1). Field of the Invention
The present invention relates generally to a method of forming a metal line utilizing an electroplating or electroless plating technique.
2). Discussion of Related Art
A semiconductor chip usually comprises an integrated circuit of semiconductor electrical components which are connected to one another by a network of metal lines. The semiconductor chip is usually manufactured by forming the electrical components first. The electrical components include transistors, resistors, diodes, capacitors, etc. Each electrical component has one or more surfaces to which electrical connection has to be made. Various techniques exist for making contact with these surfaces. One such technique for making contact is by forming a via such as a tungsten plug via on each of the surfaces. The vias extend through a dielectric over the components and terminate at a surface of the dielectric. Opposing terminating ends of the vias are then interconnected with a network of metal lines to create an integrated circuit of electrical components. More vias are in certain instances formed on the metal lines and terminating ends of these vias are also interconnected in a similar manner.
A conventional technique which is used to form these metal lines is by electroplating. A seed layer of metal, typically copper, is located on the vias. A photoresist is then deposited on the metal seed layer, and patterned so that gaps are defined above the vias in the photoresist. More of the metal in the form of a metal plating is then deposited within the gap utilizing a bias voltage with the metal seed layer acting as a layer on which the metal easily forms. FIGS. 1a to 1i illustrate a conventional electroplating technique of the aforementioned kind, with some existing problems associated therewith.
FIG. 1a shows a substrate 110 having two tungsten vias 112 and 114. The vias 112 and 114 extend upwardly from electrical components or metal lines interconnecting electrical components and terminate at a surface of the substrate 110.
FIG. 1b shows the structure of FIG. 1a after an intermediate metal layer 116 is formed on the substrate 110 and the vias 112 and 114. The intermediate metal layer 116, as will be seen in FIG. 1f, serves as a conductor for supplying an electroplating voltage.
FIG. 1c shows the structure of FIG. 1b after a metal seed layer 118 is formed on the intermediate metal layer 116. The metal seed layer 118, as will be seen in FIG. 1f, serves as a layer on which an electroplated metal easily forms. Since the metal seed layer 118 interconnects the vias 112 and 114, the metal seed layer may have to be etched, as will be seen in FIG. 1h, to isolate at least some of the vias 112 and 114 from one another.
FIG. 1d shows the structure of FIG. 1d after a photoresist layer 120 is formed on the metal seed layer.
FIG. 1e shows the structure of FIG. 1d after the photoresist layer 120 has been patterned. The photoresist layer 120 is patterned so that a gap 122 is formed over the via 112 and a gap 124 is formed over the via 114.
FIG. 1f shows the structure of FIG. 1e after metal platings 126 and 128 are formed in the gaps 122 and 124 respectively. Each metal platings 126 or 128 is formed by submerging the structure of FIG. 1e within a metal solution and applying a bias voltage to the intermediate metal layer 116. The metal platings 126 or 128 then form on the seed layer 118. The technique of forming the metal platings 126 and 128 is known as "electroplating".
FIG. 1g shows the structure of FIG. 1f after removal of the photoresist layer 120. The photoresist is then stripped to leave the metal platings 126 and 128 intact.
FIG. 1h shows the structure of FIG. 1h after etching the metal seed layer 118. During etching of the metal seed layer the metal platings 126 and 128 recede by a distance 130 which is equal to a thickness 132 of the metal seed layer 118. Each metal plating 126 or 128 thus reduces in height by an amount which is equal to the thickness of the metal seed layer 118 and recudes in width by an amount which is equal to twice the thickness of the metal seed layer 118.
FIG. 1i shows the structure of FIG. 1h after the intermediate metal layer 116 is partially etched with a selective etch which only removes the material that the intermediate metal layer 116 is made of. The vias 112 and 114 are so isolated from one another to finalize the formation of a metal line 134 and 136 on each of the vias 112 and 114 respectively.
Thus what is required is a method of electroplating a metal line on a seed layer, wherein the seed layer is not subsequently etched with resulting damage to the metal line.